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pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard pmc-sierra, inc. 105 - 8555 baxter place burnaby, bc canada v5a 4v7 604 .415.6000 PM6541 e1xc-evbd e1xc evaluation daughterboard issue 1: december 1997
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard i contents 1 overview...............................................................................................1 2 functional description ................................................................. 2 2.1 block diagram ......................................................................... 2 2.2 bus transceivers ................................................................... 2 2.3 decode logic ........................................................................... 3 2.4 dip switches ............................................................................. 3 2.5 clock dpll................................................................................. 3 2.6 oscillators .............................................................................. 3 2.7 e1xc devices............................................................................. 4 2.8 "csu" connection blocks .................................................... 4 2.9 transmit/receive interface ............................................... 5 3 interface description .................................................................... 6 3.1 edge connector interface ................................................ 6 3.2 header connections............................................................. 7 3.2.1 external signal header ........................................... 8 3.2.2 dpll header ................................................................... 8 3.2.3 e1xc headers ................................................................9 3.2.4 prototype chip select header ............................ 10 3.3 dip switches ........................................................................... 11 4 physical description .................................................................... 12 4.1 characteristics ................................................................... 12 4.2 layout ....................................................................................... 13
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard ii 5 d.c. characteristics ...................................................................... 14 6 implementation description ....................................................... 15 6.1 bus transceivers ................................................................. 15 6.2 decode logic ......................................................................... 16 6.3 clock pll and dip switches.............................................. 18 6.4 e1xc ........................................................................................... 22 6.5 "csu" dips and jumpers....................................................... 22 6.6 transmit/receive interfaces........................................... 24 7 e1xc daughterboard firmware description ....................... 25 8 stock list........................................................................................... 35 9 references ....................................................................................... 41 appendix 1: component placement diagram.................................... 42 appendix 2: schematics ............................................................................ 43
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 1 1 overview the PM6541 e1xc evbd evaluation daughterboard allows for the test, evaluation and demonstration of the pmc pm6341 e1xc device. it is also compatible with the pm4341 t1xc device. this daughterboard can be used standalone with up to two e1xc devices but has been especially designed to mate with the pmc pm1501 evmb evaluation motherboard to form a complete evaluation system. all required decoding logic is provided on the e1xc evbd daughterboard to give the evmb direct access to all registers of both e1xc devices. all of the principal connections to both devices have been brought out to header strips for convenient test access. e-1 digital interfaces are provided on a header strip and bnc or mini-bantam connectors are provided for e-1 analog signals. both 75 w and 120 w interfaces are provided. the backplane interfaces of each device are accessible through header strips and the devices can be interconnected back to back, effectively creating a jitter-attenuating format converter by dropping in shorting connectors into specific dip sockets. clocks for the backplane are provided by a t1/cept digital trunk dpll which provides a synchronized 1.544 mhz, 2.048 mhz, or 4.096 mhz signal. the pll can be easily bypassed to allow direct drive of the backplane with an appropriate oscillator. a prototype area has been provided for breadboarding more complex applications. the e1xc evbd evaluation daughterboard is configured, monitored, and powered through an edge connector that is designed to mate with the evmb evaluation motherboard
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 2 2 functional description 2.1 block diagram 96 pin male din connector decode logic e1xc east e1xc west headers osc osc clock/pll clock hdr dip sw. east tx / rx interface west tx / rx interface bus transceivers osc figure 1: block diagram 2.2 bus transceivers bus transceivers are provided at the connector interface to prevent excessive loading of the 68hc11 on the evmb evaluation motherboard. in addition they provide some measure of isolation for the daughterboard and protection for other external signals such as the extclk and extfp inputs.
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 3 2.3 decode logic decode logic is provided on the daughterboard to give memory mapped access to all of the registers within both e1xcs. registers within the "east" e1xc are accessible starting at address c000h. registers within the "west" e1xc are accessible starting at address c100h. additional chip selects are provided for addresses c200h-c2ffh and c300h-c3ffh for use on the prototype area. 2.4 dip switches the dip switch settings control the operational modes of the mt8940 dpll device that is used to generate the backplane clock. access to the enable inputs for the various clock outputs is also provided through these switches. 2.5 clock dpll the mt8940 t1/cept digital trunk dpll can provide a number of different clocks with different methods of synchronization, depending upon its mode setting, which can be used to drive the backplane interface of the e1xcs. the device can output 1.544 mhz, 2.048 mhz, and 4.096 mhz clocks in true or complement format. the dpll can be allowed to free-run or it can be synchronized to the receive frame pulses of either e1xc. pll control is accomplished with the dip switches connected to the inputs. 2.6 oscillators up to four oscillators can be used on the e1xc evbd daughterboard depending upon the choice of configuration. the e1xc devices require a 49.152 mhz clock if all of the device's features are to be utilized. although two oscillator sockets are provided, only a single oscillator is necessary if two e1xc devices are used. the insertion of a jumper (j25) will join the two e1xc xclk inputs together to allow the single clock to drive both devices. if a t1xc device is used in place of one of the e1xc devices then the jumper must be removed to isolate each clock line and a 37.056 mhz oscillator is used to drive the t1xc xclk input. the mt8940 dpll device requires two oscillators to drive internal dplls, one at 12.355 mhz, and the other at 16.384 mhz. if the mt8940 is removed from the daughterboard, then these oscillators can be replaced with ones directly compatible with the backplane rate. each oscillator output is directly accessible at header pins, allowing connections to be made by connecting jumpers to the e1xc devices.
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 4 2.7 e1xc devices up to two e1xc devices can be placed on the daughterboard at a time. each device runs independent of the other, except when explicit connections are made through the header strips (i.e. when configured as a jitter attenuating format converter). all internal registers are individually accessible and each device has been set up with individual receiver, transmitter and backplane access through headers and connectors. a full description of the e1xc device is beyond the scope of this document. for more information, refer to the pm6341 e1xc datasheet. 2.8 "csu" connection blocks while the main purpose of the evaluation daughterboard is to provide unrestricted access to all of the features of the e1xc device, one application is conveniently provided which allows easy evaluation of most of the features of the device. by plugging in shorting jumpers into the two 16 pin csu dip sockets (u5 and u6) on the daughterboard, the two e1xcs are connected back to back to implement a jitter- attenuating format converter (a function often implemented within a csu) as described in the e1xc datasheet. these csu dip socket jumpers make almost all of the necessary connections except for the signals brclk, brfpi, and btclk. connections for these signals are made through e-w and w-e jumper blocks j19, j20, j21, j22, j23, and j24. by installing jumper connections between pin 1 and pin 2 of jumper blocks j19 and j20, between pin 3 and pin 4 of each of jumper blocks j21, j22, j23, j24, and between pin 2 and 3 of jumper block j30, a "csu" like application can be implemented where the 2.048 mhz clock for the backplane between the two e1xc devices is provided by the mt8940, which in turn is locked to the recovered clock provided by e1xc #1. variations of this application can be explored by using the other options provided on the jumper blocks. connections are provided for 2.048 mhz and externally supplied backplane clock rates.
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 5 pm6341 e1xc btpcm btsig btfp btclk brfpi brclk brpcm brsig brfpo rclko rfp tap tan tc ras ref rrc #1 e-1 transmit avd + e-1 receive avs avs pm6341 e1xc btpcm btsig btfp btclk brfpi brclk brpcm brsig brfpo rclko rfp tap tan tc ras ref rrc #2 e-1 transmit avd + e-1 receive avs avs c u s t o m e r n e t w o r k xclk xclk 37.056mhz figure 2: jitter attenuating "csu" application hookup 2.9 transmit/receive interface the daughterboard provides three different types of interfaces for the transmit and receive signals. the two standard analog interfaces provided are a 120 ohm mini- bantam interface and a 75 ohm bnc interface. the transmit mini-bantams are terminated with a 200 ohm resistor on the tn/rn pins to prevent an excessive voltage kick when mini-bantam plugs are inserted or removed. the bnc connector barrel can optionally be terminated with a resistor to ground, or grounded directly, by stuffing a resistor or shorting strap in locations r15, r16, r17, and r18. the daughterboard is shipped with these 4 locations empty, thereby providing a 75? bnc interface. the third interface provided is strictly digital and brings out all of the e1xc's digital e-1 signals to header pins for easy test access. when the digital interface is used each e1xc's analog receiver can be powered down by moving the jumper on jumper block j31 or j32.
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 6 3 interface description 3.1 edge connector interface the edge connector interface is made up of a male 96 pin din of which 64 pins are actually used. it consists of signals appropriate to read and write to the registers of the devices on the daughterboard, and it provides the necessary power and ground. the connections have been specially designed to mate with pmc's pm1501 evmb evaluation motherboard. ttl signal levels are used on this interface. signal name type pin function ale o c1 address latch enable. when high, identifies that address is valid on ad[7:0]. e o c2 microprocessor clock rwb o c3 active low write, active high read enable rstb o c4 active low h/w reset a[15] o c5 address bus bit 15 a[14] o c6 address bus bit 14 a[13] o c7 address bus bit 13 a[12] o c8 address bus bit 12 a[11] o c9 address bus bit 11 a[10] o c10 address bus bit 10 a[9] o c11 address bus bit 9 a[8] o c12 address bus bit 8 ad[7] i/o c13 multiplexed address/data bus bit 7 ad[6] i/o c14 multiplexed address/data bus bit 6 ad[5] i/o c15 multiplexed address/data bus bit 5 ad[4] i/o c16 multiplexed address/data bus bit 4 ad[3] i/o c17 multiplexed address/data bus bit 3 ad[2] i/o c18 multiplexed address/data bus bit 2
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 7 ad[1] i/o c19 multiplexed address/data bus bit 1 ad[0] i/o c20 multiplexed address/data bus bit 0 pa3 o c21 68hc11 processor port a bit 3 pa4 o c22 68hc11 processor port a bit 4 pa5 o c23 68hc11 processor port a bit 5 pa6 o c24 68hc11 processor port a bit 6 pd2 i c25 miso. master in slave out of port d acting as spi. pulled up on motherboard. pd3 o c26 mosi. master out slave in of port d acting as spi. pulled up on motherboard. pd4 o c27 sck. serial clock of port d acting as spi. pulled up on motherboard. pd5 o c28 ss. slave select of port d acting as spi active low. pulled up on motherboard. irq i c29 maskable interrupt xirq i c30 non maskable interrupt disb i c31 evmb memory disable. pulling this signal low will disable mpu access to the evmb's on-board ram and eprom. sp o c32 spare gnd o a1- a28 ground +5v o a29- a32 +5 volts 3.2 header connections all e1xc functional pins are connected to male header strips to provide as much access as possible. these headers may be used as probe points or as a means to build sample applications by making appropriate connections between points. each e1xc can run in isolation of the other, thus any application, other than the default sample "csu", will require header connections to be made.
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 8 3.2.1 external signal header this header is provided to accept an external clock and framing pulse source. these inputs are then buffered for use on the board. external clock sources must be buffered through this header to avoid possible damage to the e1xcs or dpll. signal type ref. description extfp i j26-2 external framing pulse input extclk i j26-4 external clock input bextfp o j27-1 buffered external framing pulse bextclk o j27-2 buffered external clock 3.2.2 dpll header this header is provided to give access to the clock generating mt8940 dpll chip as well as provide direct oscillator access. all of the major dpll outputs are brought out to this header even though they may be of limited use with the e1xc (e.g. the 4.096 mhz clock). signal type ref. description fpin i j29-2 1.544 mhz framing pulse input to mt8940. c8kb i/o j29-1 2.048 mhz framing pulse in/out (mode dependent). gfp i/o j29-3 8 khz framing pulse output from the mt8940. note that this active low output signal is derived from the 16.388 mhz clock and has a 244ns pulse width. c1m5 o j29-4 1.544 mhz output clock from mt8940. c1m5b o j29-5 inverted c1m5 clock. c2m o j29-6 2.048 mhz output clock from mt8940. c2mb o j29-7 inverted c2m clock. c4m o j29-8 4.096 mhz output clock from mt8940. c4mb o j29-9 inverted c4m clock.
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 9 c16m o j29-10 direct access to 16.388 mhz clock driving the mt8940. this pin is mainly provided for direct oscillator access. if the mt8940 is not used the 16.388 mhz clock can be replaced by a 2.048 mhz clock with access to the clock signal provided by this pin. c12m o j29-11 direct access to 12.355 mhz clock driving the mt8940. this pin is mainly provided for direct oscillator access. if the mt8940 is not used the 12.355 mhz clock can be replaced by a 1.544 mhz clock with access to the clock signal provided by this pin. gnd g j29-12 mt8940 dpll header ground reference. 3.2.3 e1xc headers a number of headers are provided which give direct access to the main functional pins on the e1xcs. both devices on the daughterboard have the same pins brought out to headers and every effort has been made to insure that all headers are symmetrical with both devices. the e1xcs are uniquely identified by an east/west designation. the following table gives a brief description of the e1xc signals. for a more detailed description of the e1xc device, refer to the e1xc datasheet. signal type ref (e) ref (w) description tap o j9-1 j10-1 transmit analog positive pulse tan o j9-2 j10-2 transmit analog negative pulse ras i j9-3 j10-3 receive analog signal ref i/o j9-4 j10-4 receive reference gnd g j9-5 j10-5 e1xc analog ground reference tclki i j15-1 j16-1 transmit clock input tclko o j15-2 j16-2 transmit clock output tdp/tdd o j15-3 j16-3 transmit digital positive line pulse/ transmit digital ds-1 signal tdn/tflg o j15-4 j16-4 transmit digital negative line pulse/ transmit fifo flag tdlclk/ tdludr o j15-5 j16-5 transmit data link clock/ transmit data link underrun tdlsig/ tdlint i/o j15-6 j16-6 transmit data link signal/ transmit data link interrupt gnd g j15-7 j16-7 e1xc digital transmit ground reference
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 10 rdlclk/ rdleom o j13-1 j14-1 receive data link clock/ receive data link end of message rdlsig/ rdlint o j13-2 j14-2 receive data link signal/ receive data link interrupt rclki i j13-3 j14-3 receive line clock input rdp/ rdd/ sdp i/o j13-4 j14-4 receive digital positive line pulse/ receive digital ds-1 signal/ sliced positive line pulse rdn/ rlcv / sdn i/o j13-5 j14-5 receive digital negative line pulse/ receive line code violation indication/ sliced negative line pulse gnd g j13-6 j14-6 btpcm/ btdp i j11-4 j12-4 backplane transmit pcm/ backplane transmit positive line pulse btsig/ btdn i j11-3 j12-3 backplane transmit signaling/ backplane transmit negative line pulse btfp i j11-2 j12-2 backplane transmit frame pulse btclk i j11-1 j12-1 backplane transmit clock gnd g j11-5 j12-5 backplane transmit header ground reference brclk i j17-1 j18-1 backplane receive clock brfpi i j17-2 j18-2 backplane frame pulse input brpcm/ brdp o j17-3 j18-3 backplane receive pcm/ backplane receive positive line pulse brsig/ brdn o j17-4 j18-4 backplane receive signaling/ backplane receive negative line pulse brfpo o j17-5 j18-5 backplane frame pulse output rdpcm/ rpcm o j17-6 j18-6 recovered decoded pcm/ recovered pcm rclko o j17-7 j18-7 recovered pcm clock output rfp o j17-8 j18-8 receive frame pulse gnd g j17-9 j18-9 backplane receive ground reference 3.2.4 prototype chip select header two unused chip selects from the decoding logic are provided on a header near the prototype area.
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 11 signal type ref. description spare1_csb o j28-1 spare csb pin address (c2xx) spare2_csb o j28-2 spare csb pin address (c3xx) 3.3 dip switches one 8 bit dip switch is provided on the daughterboard. this switch controls the operating modes of mt8940 pll chip and the output enables for the various clock outputs. when open, each bit line is pulled high. when closed, the bit lines are individually pulled to ground. for a brief description of the mt8940 operating modes, consult the tables in the clock pll implementation description section. switch id mapping clock 1 ms0 clock 2 ms1 clock 3 ms2 clock 4 ms3 clock 5 enc2o clock 6 encv clock 7 enc4o clock 8 unused
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 12 4 physical description 4.1 characteristics the e1xc evbd is an evaluation board that allows the e1xc device to be feature tested and evaluated for various applications. while the daughterboard can be used standalone with a limited feature set, it has been especially designed to link with pmc's evmb (evaluation motherboard). the evmb controller board provides a microprocessor to read and write to all of the e1xc's internal registers allowing configuration, control and set-up of the various modes of e1xc operation. the e1xc evbd is laid out for convenient bench top use for test or demonstration purposes. it is provided with rubber feet that are placed to avoid pcb flexing. pin headers provide easy access to all signals necessary during device testing. a t1/cept digital pll is installed to provide the necessary 2.048 mhz backplane rate. external pins allow access when using an externally generated backplane clock. ground pins for scope probes are conveniently provided and distributed. simple configuration into the example csu application is provided. the dip switches, pin headers, and interface connections are labeled on the silkscreen for easy identification and ample prototype area is provided. the size of the e1xc evbd is constrained to 8.5 x 6.5 inches and, when mated with the evmb card, will fit into a standard three ring binder.
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 13 4.2 layout 96 pin male din bus transceivers mini-bantam mini-bantam mini-bantam mini-bantam bnc bnc bnc bnc e1xc #1 (east) e1xc #2 (west) prototype area transformer transformer tx/rx header backplane headers csu config dips oscillators mt8940 8940 hdr 8940 dip sw external clk/fp bantam r/c bantam r/c e1xc #2 osc glue logic e-w jumpers backplane headers w-e jumpers clk e1xc #1 osc rxanalog power rxanalog power tx/rx header figure 3: board layout
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 14 5 d.c. characteristics symbol parameter min max units test conditions v 5dc +5v dc power supply voltage 4.5 5.5 v i 5dc +5v dc power supply current 3a v 5dc = 5.0 v + 10% t a ambient temperature 050cv dc = 5.0 v + 10%
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 15 6 implementation description the e1xc evbd (PM6541) is the t1xc evbd (pm4541) with different stuffing options. the following are the differences between the two products: 1.) two pm6341s are stuffed instead of two pm4341s. 2.) oscillator u1 is not stuffed. 3.) socket u2 is stuffed with a 49.152 mhz oscillator. 4.) several resistor values are changed: r4 = r9 = 523 w (1%) r3 = r8 = 4.53 k w (1%) r20 = r22 = 1 k w (5%) 5.) stuff c1 and c4 with a 1 nf capacitor and a 47 w resistor in series. the e1xc evbd should be shipped with header shunts between the following pins: j25 - pins 1 and 2 j19 - pins 3 and 4 j20 - pins 3 and 4 j21 - pins 5 and 6 j22 - pins 5 and 6 j23 - pins 5 and 6 j24 - pins 5 and 6 j22 - pins 5 and 6 j30 - pins 1 and 2 j31 - pins 1 and 2 j32 - pins 1 and 2 6.1 bus transceivers bus transceivers have been used on the daughterboard to minimize the loading presented to the motherboard microprocessor. two 74hct244's buffer all eight upper address bits, the microprocessor control signals, and the external clock and framing pulse inputs. a single 74hct245 provides the bi-directional buffering of the
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 16 multiplexed address/data bus. all motherboard signals from the 96-pin din connector have been tied through sips to insure proper standalone operation. the standard techniques outlined in the evmb datasheet for implementing the decoding and buffering has been followed. 6.2 decode logic the decode logic provides the address mapping of all internal registers of both e1xc's as well as providing generation of the required rdb and wrb signals. again the implementation of the decode logic has followed the techniques outlined in the evmb datasheet. e1xc #1 (east) is mapped starting at address c000h and e1xc #2 (west) is mapped starting at address c100h. two unused chip selects, active for address ranges c200-c2ffh and c300-c3ffh, are available for use on the prototype section. the full register map is given below: east e1xc west e1xc description c000h c100h e1xc receive options c001h c101h e1xc receive backplane options c002h c102h e1xc datalink options c003h c103h e1xc receive interface configuration c004h c104h e1xc transmit interface configuration c005h c105h e1xc transmit backplane options c006h c106h e1xc transmit framing options c007h c107h e1xc transmit timing options c008h c108h e1xc master interrupt source c009h c109h e1xc receive ts0 data link enables c00ah c10ah e1xc master diagnostics c00bh c10bh e1xc master test c00ch c10ch e1xc revision/chip id c00dh c10dh e1xc master reset c00eh c10eh e1xc phase status word (lsb) c00fh c10fh e1xc phase status word (msb) c010h c110h cdrc tsb configuration c011h c111h cdrc tsb interrupt enable c012h c112h cdrc tsb interrupt status c013h c113h alternate loss of signal c014h c114h xpls tsb line length configuration c015h c115h xpls tsb control/status c016h c116h xpls tsb code indirect address c017h c117h xpls tsb code indirect data c018h c118h djat tsb interrupt status
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 17 c019h c119h djat tsb reference clock divisor (n1) control c01ah c11ah djat tsb output clock divisor (n2) control c01bh c11bh djat tsb configuration c01ch c11ch elst tsb configuration c01dh c11dh elst tsb interrupt enable/status c020h c120h frmr tsb framing alignment options c021h c121h frmr tsb maintenance mode options c022h c122h frmr tsb framing status interrupt enable c023h c123h frmr tsb maintenance/alarm status interrupt c024h c124h frmr tsb framing status interrupt indication c025h c125h frmr tsb maintenance/alarm status interrupt indication c026h c126h frmr tsb framing status c027h c127h frmr tsb maintenance /alarm status c028h c128h frmr tsb international/national bits c029h c129h frmr tsb extra bits c02ah c12ah frmr tsb crc error count - lsb c02bh c12bh frmr tsb crc error count - msb c02ch c12ch ts16 ais alarm status c030h c130h tpsc tsb configuration c031h c131h tpsc tsb p access status c032h c132h tpsc tsb channel indirect address/control c033h c133h tpsc tsb channel indirect data buffer c034h c134h xfdl tsb configuration c035h c135h xfdl tsb interrupt status c036h c136h xfdl tsb transmit data c038h c138h rfdl tsb configuration c039h c139h rfdl tsb interrupt status/control c03ah c13ah rfdl tsb status c03bh c13bh rfdl tsb receive data c040h c140h sigx tsb configuration c041h c141h sigx tsb p access status c042h c142h sigx tsb channel indirect address/control c043h c143h sigx tsb channel indirect data buffer c044h c144h tran tsb configuration c045h c145h tran tsb transmit alarm/diagnostic control c046h c146h tran tsb international/national control c047h c147h tran tsb extra bits control
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 18 c048h c148h pmon tsb control/status c049h c149h pmon tsb fer count c04ah c14ah pmon tsb febe count (lsb) c04bh c14bh pmon tsb febe count (msb) c04ch c14ch pmon tsb crc count (lsb) c04dh c14dh pmon tsb crc count (msb) c04eh c14eh pmon tsb lcv count (lsb) c04fh c14fh pmon tsb lcv count (msb) c059h c159h rslc tsb configuration c05dh c15dh rslc tsb interrupt enable/status dout read cycle write cycle bale brwb ba[15:8] bad[7:0] t1xc_wrb t1xc_rdb hct245 dir t1xc_csb be_clock a[7:0] ba="c0"; brwb=1 ba "c0"; brwb=1 ba="c0"; brwb=0 ba "c0"; brwb=0 dout a[7:0] din a[7:0] din a[7:0] figure 4: decode logic waveforms 6.3 clock pll and dip switches one mitel mt8940 provides all clocks necessary to drive the 2048 kbit/s backplane rate supported by the e1xc. the mt8940 is a dual digital pll which can provide timing and synchronization signals for t1 or cept transmission links and the st- bus . the first pll provides the t1 clock (1.544 mhz) synchronized to an input framing pulse. the second pll provides cept or st-bus timing signals synchronized to an internal or external framing pulse signal. for a more detailed
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 19 description of the device, refer to the datasheet on the mt8940 in the mitel semiconductor databook. all outputs of the mt8940 are either brought out to header blocks or routed to the csu connector dip sockets. a single 8-position dip switch provides control over the mode of the mt8940 device as well as control over the output clock enables. if the mt8940 is not used, it can be removed from the daughterboard and its oscillators can be replaced with 1.544 mhz and 2.048 mhz devices. the pll oscillator clock outputs are conveniently brought out to the header strip for use on the daughterboard. the mapping of the dip switches to the mt8940 ports is as follows: switch id label mapping sw1-1 ms0 ms0 (mode select '0') sw1-2 ms1 ms1 (mode select '1') sw1-3 ms2 ms2 (mode select '2') sw1-4 ms3 ms3 (mode select '3') sw1-5 enc2 enc20 (active high enable control for pins c2o and c2ob ) sw1-6 encv encv (active high enable control for pins cv and cvb ) sw1-7 enc4 enc40 (active high enable control for pins c4o and c4ob ) sw1-8 unused setting these switches selects the operating mode for the mt8940, as described below: mode # ms[0:3] dpll #1 operating mode dpll #2 operating mode 0 0000 normal mode: generates the 1.544 mhz t1 clock synchronized to the falling edge of the input framing pulse. externally applied 4.096 mhz. clock and 8 khz. frame pulse, properly phase related, are used to generate the 2.048 mhz output clock. 1 0001 normal mode operates as above. normal mode: generates the cept (st- bus) timing signals locked to the 8 khz input signal (c8kb)
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 20 2 0010 normal mode operates as above. externally applied 4.096 mhz. clock is used to generate the 2.048 mhz output clock and 8 khz frame pulse. 3 0011 default config normal mode operates as above. normal mode generates the cept (st- bus) timing signals locked to the 8 khz input signal (c8kb) 4 0100 divide-1 mode: divides the cvb input signal by 193. the divided output is connected to dpll #2 externally applied 4.096 mhz. clock and 8 khz. frame pulse, properly phase related, are used to generate the 2.048 mhz output clock. 5 0101 divide-1 mode operates as above single clock-1 mode: provides the cept/st-bus compatible timing signals locked to an 8 khz. internal signal provided by dpll #1. 6 0110 divide-1 mode same as 'mode 2' 7 0111 divide-1 mode single clock-1 mode 8 1000 normal mode same as 'mode 0' 9 1001 normal mode f0b becomes an input. dpll #2 provides the st- bus signals locked onto f0b input only if it is 16 khz. 10 1010 normal mode same as 'mode 2' 11 1011 normal mode free run mode provides the cept/st-bus compatible timing and framing signals with no external inputs other than the master clock.
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 21 12 1100 divide-2 mode: divides the cvb input by 256. the divided output is connected to dpll #2 same as 'mode 0' 13 1101 divide-2 mode single clock-2 mode: provides the cept/st-bus signals locked to the 8 khz. internal signal provided by dpll #1 14 1110 divide-2 mode same as 'mode 2' 15 1111 divide-2 mode single clock-2 mode
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 22 6.4 e1xc two e1xcs can be socketed into the daughterboard. each is individually accessible and can run independently of the other. all pins except for the microprocessor interface and power pins are connected to header strips for easy test equipment access. analog receive power pin ravd is connected to a jumper to enable tying to either ground or power. tying this pin to ground will disable the internal rslc tsb, reducing the power consumed. tying the ravd pin to vcc enables the normal operating mode. all other power pins are appropriately decoupled and all inputs are tied high through 10 k w resistors sips. for a more detailed description of the e1xc and its features, refer to the e1xc standard product datasheet. 6.5 "csu" dips and jumpers normally, the two e1xcs run independently of each other except when explicit connections are made between the two devices. to facilitate testing of a simple application involving two devices appropriate control signals have been wired to two 16 pin dip sockets and six jumpers to enable hooking up the e1xcs in a "csu"-like application.
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 23 btpcm brfpi brclk brpcm btsig btfp btclk brsig brfpo rclko rfp tap tan e-1 transmit interface ras ref e-1 receive interface "n e t w o r k" e1xc #1 (east) brfpi brclk brpcm brsig brfpo rclko rfp btpcm btsig btfp btclk e1xc #2 (west) gfp bextfp j20 c1m5 c2m bextclk j24 j21 gfp bextfp j19 j22 c1m5 c2m bextclk j23 e-1 transmit interface e-1 receive interface ref ras tan tap c u s t o m e r ew csu jumper we csu jumper j30 rfp figure 5: csu circuit overview both e1xcs are connected in a symmetrical fashion and most connections are completed by installing shorting bar jumpers into the two 16 pin dip sockets labeled for the csu set-up. the remaining unconnected signals are brclk, brfpi, and btclk. by installing jumpers across pins 1 and 2 of each of jumper blocks j19 and j20, between pins 3 and 4 of each of the jumper blocks j21, j22, j23, j24, and between pin 2 and 3 of jumper block j30, a "csu" like application can be implemented where the 2.048 mhz clock for the backplane between the two e1xc devices is provided by the mt8940, which in turn is locked to the recovered clock provided by e1xc #1. bits 1 and 2 of sw1 must be closed; the remaining bits
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 24 open. by appropriately making jumper connections to the other available clock options, the backplane can be run at different rates, such 2.048 mhz or at an externally supplied clock rate. 6.6 transmit/receive interfaces three different transmit and receive interfaces are provided on the daughterboard. the digital interface can be used by connecting to the two header blocks immediately adjacent to each e1xc. header blocks j13 and j15 provide the digital interface for the east e1xc while headers j14 and j16 provide the interface for the west e1xc. before making use of these pins, the analog receiver of each e1xc should be disabled. this is done by moving the jumpers on j31 and j3, which provide power to ravd, to the grounding position. two e-1 analog interfaces are also provided. both the transmit and receive e-1 interfaces on each e1xc can be connected to either a mini-bantam or bnc connector. the analog transmit and receive interface are passed through a 1:1.36 and 2:1 transformer, respectively, and then connected to either bantam or bnc connectors. the transmit mini-bantam is terminated with a 100 ohm resistor to prevent "kick-back" when a plug is inserted or removed from the jack. the receive bnc interface is a standard 75 ohm coax with stuffing options for ground or resistor connections across the shield (or barrel).
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 25 7 e1xc daughterboard firmware description the evmb evaluation board provides a serial interface for hooking up a standard "vt100" type terminal. the rf2 serial 25-pin d-type connector on the evmb is configured as a dce, 9600 baud, 8 bit, no parity, one stop bit. connecting a terminal to this port, setting switch 2 on the mode switch bank to closed and pressing the reset switch on the evmb will enable console control. when the system is started cold or after a hardware reset, the first output to the console will be the forth kernel identification followed by a prompt: max-forth vx.x > the first commands that should be downloaded into the system after a cold boot should be (note: each line must be terminated with a "carriage return"; the text within parenthesis are comments and do not have to be typed in): hex ( set up hex number base ) 100 tib ! ( relocate text input buffer to eram address 100h ) 50 tib 2+ ! ( define 80 character text input buffer length ) 200 dp ! ( set up dictionary pointer ) after inputting each of these commands followed by a carriage return, the forth interpreter should respond with an "ok" signifying it has accepted it. any failure to properly input these set-up statements will be characterized by a "?" response from the interpreter and/or by errors when inputting any subsequent data. further, if an error occurred while entering the commands to relocate the text input buffer or redefine its length, the text buffer will be unable to accept more than the default 16 characters per line input. the following forth code was developed for the e1xc daughterboard and presented here as an example. to set-up the e1xc, all that is minimally required is the above evmb initialization words, the register address constant definitions, and the rd and wr routines. the remaining words are useful for exercising the more advanced features of the e1xc. variable dev variable tsb variable m variable n variable t
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 26 ( define base addresses) c000 constant ee1xcnorm c080 constant ee1xctest c100 constant we1xcnorm c180 constant we1xctest 10 constant cdrc 14 constant xpls 18 constant djat 1c constant eelst 20 constant frmr 30 constant pcsc 34 constant xfdl 40 constant esigx 44 constant tran 48 constant pmon 5c constant rslc 00 constant rxopt 01 constant rxbp 02 constant rxdl 03 constant rxif 04 constant txif 05 constant txbp 06 constant txfo 07 constant txto 08 constant intstat 0d constant mdiag 0d constant mreset ( ### general purpose routines ### ) : rd ( addr --- data ) c@ ; : prt ( data --- ) ." = " u. ." hex" cr ; : wr ( addr data --- ) swap c! ; : east ee1xcnorm dev ! ;
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 27 : west we1xcnorm dev ! ; : ad ( tsb offset --- addr ) ( calculate the absolute address of normal register ) ( assumes dev has been set to ee1xcnorm or we1xcnorm ) + dev @ + ; : wrbit ( addr data bitpos --- ) ( modify a single bit based upon "bitpos" mask ) dup rot 01 and * ff rot - 2 pick rd and or wr ; : wrind ( offset base data --- ) ( perform sigx or pcsc indirect write ) ( "offset" is the indirect address ) ( "base" is the sigx or pcsc base address ) ( "data" is the value to be written ) swap tsb ! ( store base ) tsb @ 3 + c! ( write data ) tsb @ 2 + swap 7f and wr ( write offset with r/w low ) 10 0 do tsb @ 1 + rd 80 < if leave then ( leave if not busy ) i 9 > if cr ." busy still high " cr leave then loop ; : rdind ( offset base --- data ) ( perform sigx or pcsc indirect read ) ( "offset" is the indirect address ) ( "base" is the sigx or pcsc base address ) ( "data" is the value to read ) tsb ! ( store base ) tsb @ 2 + swap 80 or wr ( write addr with r/w high ) 10 0 do tsb @ 1 + rd 80 < if leave then ( leave if not busy ) i 9 > if cr ." busy still high" cr leave then loop tsb @ 3 + rd ; ( read data ) ( ### config ### ) ( the "data" value is written to the appropriate bit ) : sind ( data --- )
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 28 esigx 0 ad ( calc reg addr ) swap 02 wrbit ; : spcce ( data --- ) esigx 0 ad ( calc reg addr ) swap 01 wrbit ; : reset ( data --- ) mreset 0 ad ( calc reg addr ) swap 01 wrbit ; ( ### pcsc config ### ) : pind ( data --- ) pcsc 0 ad ( calc reg addr ) swap 2 wrbit ; : ppcce ( data --- ) pcsc 0 ad ( calc reg addr ) swap 1 wrbit ; ( ### tran config ### ) : txami ( data --- ) tran 0 ad ( calc reg addr ) swap 80 wrbit ; : txccs ( --- ) tran 0 ad ( calc reg addr ) dup rd 9f and wr ; : txcas ( --- ) tran 0 ad ( calc reg addr ) dup rd 60 or wr ; : gencrc ( data --- ) tran 0 ad ( calc reg addr ) swap 10 wrbit ; : crcen ( data --- ) frmr 0 ad ( calc reg addr ) swap 80 wrbit ; : ddl ( data --- ) mdiag 0 ad ( calc reg addr ) swap 4 wrbit ;
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 29 : dml ( data --- ) mdiag 0 ad ( calc reg addr ) swap 8 wrbit ; : ll ( data --- ) mdiag 0 ad ( calc reg addr ) swap 10 wrbit ; : pl ( data --- ) mdiag 0 ad ( calc reg addr ) swap 20 wrbit ; : refr ( data --- ) frmr 0 ad ( calc reg addr ) swap 04 wrbit ; : rcrce ( data --- ) frmr 0 ad ( calc reg addr ) swap 02 wrbit ; : fdis ( data --- ) tran 0 ad ( calc reg addr ) swap 08 wrbit ; : dumpsigx ( --- ) ( print sigx contents ) cr esigx 0 ad tsb ! 1 swap sind 8 2 do 10 0 do j 10 * i + tsb @ rdind 3 .r loop cr loop ; : dumppcsc ( --- ) ( print pcsc contents ) cr
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 30 pcsc 0 ad tsb ! 1 pind 6 2 do 10 0 do j 10 * i + tsb @ rdind 3 .r loop cr loop ; ( ### interrupt handling ### ) : getint ( data int --- data/2 int/2 < data mod 2> int mod 2) ( data returned only if int mod 2 = 1 ) 2 /mod swap dup 0> if rot 2 /mod 3 -roll swap else rot 2/ 2 -roll then ; : int_handle ( --- ) ( ** frmr ** ) frmr 5 ad dup rd dup 0> if ." time = " decimal t @ . hex cr swap 2+ rd swap getint 0> if ." crce" cr drop then getint 0> if ." febe" cr drop then getint 0> if ." ais = " . cr then getint 0> if ." red = " . cr then getint 0> if ." ts16aisd = " . cr then getint 0> if ." aisd = " . cr then getint 0> if ." rrma = " . cr then getint 0> if ." rra = " . cr then then drop drop
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 31 frmr 4 ad dup rd 7f and dup 0> if ." time = " decimal t @ u. hex cr swap 2+ rd swap getint 0> if ." cmfer" cr drop then getint 0> if ." smfer" cr drop then getint 0> if ." fer" cr drop then getint 0> if ." cofa" cr drop then getint 0> if ." oocmf = " . cr then getint 0> if ." oosmf = " . cr then getint 0> if ." oof = " . cr then then drop drop frmr 1 ad rd 03 and ?dup 0> if dup 1 and 0> if ." excrce " cr then 2 and 0> if ." cmfact " cr then then ( ** elst ** ) eelst 1 ad rd 2 /mod swap 0> if ." time = " decimal t @ u. hex cr 01 and 0> if ." forward" else ." backward" then space ." slip" cr else drop then ; : ih int_handle ; ( ## init sigx per-chan functions ## ) : sigx_fill ( --- )
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 32 esigx 0 ad 80 40 do dup i swap 1a wrind loop drop ; ( ## init pcsc ## ) : pcscfillind ( --- ) ( put incrementing idle code in pcsc ) 1 pind 41 20 do pcsc 0 ad i swap 0 wrind loop 60 41 do pcsc 0 ad i swap i f and 10 or wrind loop pcsc 0 ad 40 swap 0 wrind pcsc 0 ad 50 swap 0 wrind ; : pollpmon ( --- error ) ( print any non-zero contents ) ( "error" = 0 if all zero counts; 1 otherwise ) pmon 0 ad dup 1+ rd 7f and dup ( read fer ) 2 pick 2+ @ >< 3ff and dup rot or ( two byte read of febe ) 3 pick 4 + @ >< 3ff and dup rot or ( two byte read of crce ) 4 roll 6 + @ >< 1fff and dup rot or ( two byte read of lcv )
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 33 if ( if non-zero count print ) decimal t @ u. space ." lcv=" 6 .r space ." crce=" 5 .r space ." febe=" 5 .r space ." fer=" 5 .r cr hex space 1 ( return code ) else ( else do nothing ) drop drop drop drop 0 then ; ( ## monitor e1xc activity ## ) : polle1xc ( check e1xc status continuously and transfer pmon about ) ( once per second. only error conditions reported. ) 03 b026 c! ( init pactl ) 40 b025 c! ( clear rtif ) 0 t ! begin 1f 0 do begin int_handle b025 c@ 40 and 0> until ( wait for rtif ) 40 b025 c! ( clear tof ) loop t 1+! pmon 0 ad 0 wr pollpmon drop ?terminal until ; : maintest 1 ppcce 1 pind 1 sind 1 gencrc 1 crcen
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 34 polle1xc ; this document is not intended to give a full tutorial in forth, which is better covered in the many forth books available. the forth kernel on the 68hc11 on the evmb is based upon the forth-83 standard and should be upward compatible from forth-79. for a complete, detailed forth tutorial, refer to the manuals listed in the references.
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 35 8 stock list item qty reference description 1 c1, c4 not installed 2 2c2, c5 0.68 f ceramic capacitor, 0.3" spacing, 100vdc 3 2c3, c6 0.1 f ceramic capacitor, 0.3" spacing, 100vdc 4 2c7, c8 47 nf ceramic capacitor, 0.2" spacing, 100vdc 5 2c9, c10 470 nf ceramic capacitor, 0.2" spacing, 100vdc 6 25 c11, c12, c13, c14, c15, c16, c17, c18, c19, c20, c21, c22, c23, c24, c25, c26, c27, c28, c29, c30, c31, c32, c33, c34, c35 0.01 f ceramic capacitor, 0.2" spacing, 100vdc
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 36 7 4j1, j2, j3, j4 adc pc834 bantam pcb jack with cover 8 4j5, j6, j7, j8 molex 73136-5001 bnc pcb mount jack, 50 ohm impedance 9 1j9, j10, j11, j12 indus 929647-01-36 breakable male straight single row strip headers, 0.1" spacing, tin plated, 36 contacts - cut into lengths of 5 contacts each 10 1 j13, j14 indus 929647-01-36 breakable male straight single row strip headers, 0.1" spacing, tin plated, 36 contacts - cut into lengths of 6 contacts each 11 1 j15, j16 indus 929647-01-36 breakable male straight single row strip headers, 0.1" spacing, tin plated, 36 contacts - cut into lengths of 7 contacts each 12 1 j17, j18 indus 929647-01-36 breakable male straight single row strip headers, 0.1" spacing, tin plated, 36 contacts - cut into lengths of 9 contacts each 13 1 j19, j20 dual row male header strip, tin plated, 0.1" spacing, straight, 50 contacts total, indus 923866 - cut into lengths of 3 contact pairs each 14 1 j21, j22, j23, j24 dual row male header strip, tin plated, 0.1" spacing, straight, 50 contacts total, indus 923866 - cut into lengths of 4 contact pairs each 15 1 j25, j27, j28 indus 929647-01-36 breakable male straight single row strip headers, 0.1" spacing, tin plated, 36 contacts - cut into lengths of 2 contacts each 16 1 j26, j31, j32 dual row male header strip, tin plated, 0.1" spacing, straight, 50 contacts total, indus 923866 - cut into lengths of 2 contact pairs each
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 37 17 1 j29 indus 929647-01-36 breakable male straight single row strip headers, 0.1" spacing, tin plated, 36 contacts - cut into a length of 12 contacts 18 1 j30 indus 929647-01-36 breakable male straight single row strip headers, 0.1" spacing, tin plated, 36 contacts - cut into a length of 3 contacts 19 1 p1 right angle mount, 96 pin male din edge connector, winchester 96p-6033-0731-0 20 2r1, r6 1 w , 1/4 w, 5% resistor 21 r2, r7, r11, r12, r13, r14, r15, r16, r17, r18 not installed 22 1r3 r8 4.53 k w , 1/4 w, 1% resistor 23 1r4 r9 523 w , 1/4 w, 1% resistor 24 2r5, r10 1.1 k w , 1/4 w, 1% resistor 25 2 r19, r20, r21, r22 200 w , 1/4 w, 5% 26 2 r23, r24 316 k w , 1/4 w, 5% resistor 27 2 r25, r26 270 w , 1/4 w, 5% 28 2 r27, r28 330 w , 1/4 w, 5%
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 38 29 r29, r30, r31, r32, r33, r34, r35, r36, r37 not used 30 3 r38, r39, r40 10 k w , 1/8 w, 5% resistor 31 8 rn1, rn2, rn3, rn4, rn5, rn6, rn7, rn8, 10 pin 9 resistor sip C 10k w , 5% 32 1 sw1 8 position spst dip switch, grayhill 76sb08 33 6 s_t1, s_t2, s_u1, s_u2, s_u14, s_u15 14 pin dip socket 34 2 s_u3, s_u4 68 pin plcc socket, through hole, amp 821574-1 35 2 s_u5, s_u6 16 pin dip socket 36 1 s_u13 24 pin dip socket, 0.6" wide 37 2t1, t2 dual 1:2ct & 1:1.36 transformer: bh electronics 500- 1777, or pulse engineering pe64952 q7789-3 38 1 u1 not installed 39 u2 fox 49.152 mhz oscillator in half inch case, ttl levels.
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 39 40 2u3, u4 e1xc - single e-1 transceiver, pm6341 41 2u5, u6 u-link - 8 connections 42 2u7, u8 74hct244 bus transceiver 43 1 u9 74hct245 bi-directional bus transceiver 44 1 u10 74hc138 3 to 8 line demux 45 1 u11 74hc139 dual 2 to 4 line demux 46 1 u12 74hc00 quad nand gate 47 1 u13 mitel mt8940ac t1/cept pll, ceramic dip 48 1 u14 fox 16.388 mhz oscillator in half inch case, ttl levels 49 1 u15 fox 12.355 mhz oscillator in half inch case, ttl levels 50 10 sh_j19, sh_j20, sh_j21, sh_j22, sh_j23, sh_j24, sh_j25, sh_j30, sh_j31, sh_j32 header shunt 0.1" spacing, textech 41670300-p4
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 40
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 41 9 references ? pmc-910419, e1-e1xc-ds, "single cept e1 transceiver telecom standard product datasheet", april 30, 1993, issue 4 ? pmc-900602, t1-t1xc-ds, "single dsx-1 transceiver device datasheet", january 1993, issue 3 ? pmc-920235, evmb-ds, "pmc device evaluation motherboard datasheet", feb. 1992, issue 1 ? "forth: a text and reference", mahlon g. kelly, nicolas spies, prentice-hall 1986 ? "understanding forth", j. reymann, alfred publishing co., 1983 ? mitel 9191-952-005-na, "microelectronics digital communications handbook", issue 8, 1991. ? pmc-891007, t1-t1xc, "single dsx-1 transceiver device engineering document". december 1992, issue 6 ? pmc-901204, e1-e1xc, "single cept e1 transceiver device engineering document". april 1993, issue 4 ? pmc-910501, evmb, "pmc device evaluation motherboard engineering document". feb. 1992, issue 3 ? "max-forth reference manual (preliminary edition.)". new micros inc., 1601 chalk hill rd dallas, texas. tel 214 339 2204 ? pmc-971216, evaluation board graphical user interface users guide. dec. 1997, issue 1
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 42 appendix 1: component placement diagram
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 43 appendix 2: schematics
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 44 notes
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard 45 notes
pmc-sierra, inc. PM6541 e1xc-evbd telecom standard product pmc-930917 issue 1 e1xc evaluation daughterboard none of the information contained in this document constitutes an express or implied warranty by pmc-sierra, inc. as to the suf ficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchanta bility, performance, compatibility with other parts or systems, of any of the products of pmc-sierra, inc., or any portion thereof, referred to in this document. pmc-sierra, inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not l imited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. in no event will pmc-sierra, inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not pmc-sierra, inc. has been advised of the possibility of such damage. ? 1997 pmc-sierra, inc. pm-930917 (r2) ref pmc-920247 (r3) issue date: december 1997 pmc-sierra, inc. 105 - 8555 baxter place burnaby, bc canada v5a 4v7 604 .415.6000 contacting pmc-sierra, inc. pmc-sierra, inc. 105-8555 baxter place burnaby, bc canada v5a 4v7 tel: (604) 415-6000 fax: (604) 415-6200 document information: document@pmc-sierra.com corporate information: info@pmc-sierra.com application information: apps@pmc-sierra.com web site: http://www.pmc-sierra.com

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